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M34C02-LBN6T Datasheet(PDF) 5 Page - STMicroelectronics |
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M34C02-LBN6T Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 19 page 5/19 M34C02 command triggers the internal EEPROM write cycle. Acknowledge Bit (ACK) An acknowledge signal is used to indicate a successful byte transfer. The bus transmitter, whether it be master or slave, releases the SDA bus after sending eight bits of data. During the 9th clock pulse period, the receiver pulls the SDA bus low to acknowledge the receipt of the eight data bits. Data Input During data input, the memory device samples the SDA bus signal on the rising edge of the clock, SCL. For correct device operation, the SDA signal must be stable during the clock low-to-high transition, and the data must change only when the SCL line is low. Memory Addressing To start communication between the bus master and the slave memory, the master must initiate a START condition. Following this, the master sends the 8-bit byte, shown in Table 3, on the SDA bus line (most significant bit first). This consists of the 7-bit Device Select Code, and the 1-bit Read/Write Designator (RW). The Device Select Code is further subdivided into: a 4-bit Device Type Identifier, and a 3-bit Chip Enable “Address” (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is 1010b. To address the Protection Register, it is 0110b. If all three chip enable inputs are connected, up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on its Chip Enable inputs. When the Device Select Code is received on the SDA bus, the memory only responds if the Chip Select Code is the same as the pattern applied to its Chip Enable pins. The 8th bit is the read or write bit (RW). This bit is set to ‘1’ for read and ‘0’ for write operations. If a match occurs on the Device Select Code, the corresponding memory gives an acknowledgment on the SDA bus during the 9th bit time. If the memory does not match the Device Select code, it will deselect itself from the bus, and go into stand- by mode. Write Operations Following a START condition the master sends a Device Select Code with the RW bit set to ’0’, as shown in Table 4. The memory acknowledges this, and waits for an address byte. The memory responds to the address byte with an acknowledge bit, and then waits for the data byte. Writing to the memory may be inhibited if the WC input pin is taken high. Byte Write In the Byte Write mode, after the Device Select Code and the address byte, the master sends one data byte. If the addressed location is in a write protected area, the memory replies with a NoAck, and the location is not modified. If, instead, the addressed location is not in a write protected area, the memory replies with an Ack. The master terminates the transfer by generating a STOP condition. Page Write The Page Write mode allows up to 16 bytes to be written in a single write cycle, provided that they are all located in the same ’row’ in the memory: that is the most significant memory address bits (b7-b4) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as ‘roll-over’ occurs. Data starts to become overwritten (in a way not formally specified in this data sheet). The master sends from one up to 16 bytes of data, each of which is acknowledged by the memory if the WC pin is low. If the WC pin is high, the contents of the addressed memory location are not modified. After each byte is transferred, the internal byte address counter (the 4 least Table 4. Operating Modes Note: 1. X = VIH or VIL. Mode RW bit WC 1 Bytes Initial Sequence Current Address Read 1 X 1 START, Device Select, RW = ‘1’ Random Address Read 0X 1 START, Device Select, RW = ‘0’, Address 1 X reSTART, Device Select, RW = ‘1’ Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read Byte Write 0 VIL 1 START, Device Select, RW = ‘0’ Page Write 0 VIL ≤ 16 START, Device Select, RW = ‘0’ |
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