M34C02DW datasheet(3/19 Pages) STMICROELECTRONICS

Part #	M34C02DW

Description	2 Kbit Serial I짼C Bus EEPROM For DIMM Serial Presence Detect

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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M34C02

When data is read by the bus master, the bus

master acknowledges the receipt of the data byte

in the same way. Data transfers are terminated by

a STOP condition after an Ack for WRITE, and

after a NoAck for READ.

Power On Reset: VCC Lock-Out Write Protect

In order to prevent data corruption and inadvertent

write operations during power up, a Power On

Reset (POR) circuit is included. The internal reset

is held active until the VCC voltage has reached

the POR threshold value, and all operations are

disabled – the device will not respond to any

command. In the same way, when VCC drops from

the operating voltage, below the POR threshold

value, all operations are disabled and the device

will not respond to any command. A stable and

valid VCC must be applied before applying any

logic signal.

SIGNAL DESCRIPTION

Serial Clock (SCL)

The SCL input pin is used to strobe all data in and

out of the memory. In applications where this line

is used by slaves to synchronize the bus to a

slower clock, the master must have an open drain

output, and a pull-up resistor must be connected

from the SCL line to VCC. (Figure 3 indicates how

the value of the pull-up resistor can be calculated).

In most applications, though, this method of

synchronization is not employed, and so the pull-

up resistor is not necessary, provided that the

master has a push-pull (rather than open drain)

output.

Serial Data (SDA)

The SDA pin is bi-directional, and is used to

transfer data in or out of the memory. It is an open

drain output that may be wire-OR’ed with other

open drain or open collector signals on the bus. A

pull up resistor must be connected from the SDA

bus to VCC. (Figure 3 indicates how the value of

the pull-up resistor can be calculated).

Chip Enable (E2, E1, E0)

These chip enable inputs are used to set the value

that is to be looked for on the three least significant

bits (b3, b2, b1) of the 7-bit device select code.

These inputs may be driven dynamically or tied to

VCC or VSS to establish the device select code.

Write Control (WC)

A hardware Write Control (WC, pin 7) is provided

for protecting the contents of the whole memory

from erroneous erase/write cycles. The Write

Control signal is used to enable (WC=VIL) or

disable (WC=VIH) write instructions to the entire

memory area or to the Protection Register.

When WC is tied to VSS or left unconnected, the

write protection of the first half of the memory is

determined by the status of the Protection

Register.

DEVICE OPERATION

The memory device supports the I2C protocol.

This is summarized in Figure 4. Any device that

sends data on to the bus is defined to be a

transmitter, and any device that reads the data to

be a receiver. The device that controls the data

transfer is known as the master, and the other as

the slave. A data transfer can only be initiated by

the master, which will also provide the serial clock

for synchronization. The memory device is always

a slave device in all communication.

Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I

2C Bus

AI01665

VCC

CBUS

SDA

RL

MASTER

RL

SCL

CBUS

100

0

4

8

12

16

20

CBUS (pF)

10

1000

fc = 400kHz

fc = 100kHz

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