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M34C02 Datasheet(PDF) 6 Page - STMicroelectronics |
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M34C02 Datasheet(HTML) 6 Page - STMicroelectronics |
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6 / 19 page  M34C02 6/19 Figure 5. How to Set the Write Protection Figure 6. Write Mode Sequences in the Non Write-Protected Area Default EEPROM memory area state before write access to the Protect Register AI01936C Standard Array FFh Standard Array 80h 7Fh 00h Standard Array FFh Write Protected Array 80h 7Fh 00h State of the EEPROM memory area after write access to the Protect Register Memory Area BYTE WRITE DEV SEL BYTE ADDR DATA IN PAGE WRITE DEV SEL BYTE ADDR DATA IN 1 DATA IN 2 AI01941 DATA IN N ACK ACK ACK R/W ACK ACK ACK R/W ACK ACK significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition. When the master generates a STOP condition immediately after the Ack bit (in the “10th bit” time slot), either at the end of a byte write or a page write, the internal memory write cycle is triggered. A STOP condition at any other time does not trigger the internal write cycle. During the internal write cycle, the SDA input is disabled internally, and the device does not respond to any requests. Minimizing System Delays by Polling On ACK During the internal write cycle, the memory disconnects itself from the bus, and copies the data from its internal latches to the memory cells. The maximum write time (tw) is shown in Table 9, but the typical time is shorter. To make use of this, an Ack polling sequence can be used by the master. |
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