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M34C02 Datasheet(PDF) 9 Page - STMicroelectronics |
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M34C02 Datasheet(HTML) 9 Page - STMicroelectronics |
9 / 19 page 9/19 M34C02 for any other write command, the WC input needs to be held at VSS. Address and data bytes must be sent with this command, but their values are all ignored, and are treated as Don’t Care. Once the Protection Register has been written, the write protection of the first 128 bytes of the memory is enabled, and it is not possible to unprotect these 128 bytes, even if the device is powered off and on, and regardless the state of the WC input. When the Protection Register has been written, the M34C02 no longer responds to the device type identifier 0110b in either read or write mode. Read Operations Read operations are performed independently of the state of the WC pin. Random Address Read A dummy write is performed to load the address into the address counter, as shown in Figure 9. Then, without sending a STOP condition, the master sends another START condition, and repeats the Device Select Code, with the RW bit set to ‘1’. The memory acknowledges this, and outputs the contents of the addressed byte. The master must not acknowledge the byte output, and terminates the transfer with a STOP condition. Current Address Read The device has an internal address counter which is incremented each time a byte is read. For the Current Address Read mode, following a START condition, the master sends a Device Select Code with the RW bit set to ‘1’. The memory acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The master terminates the transfer with a STOP condition, as shown in Figure 9, without acknowledging the byte output. Sequential Read This mode can be initiated with either a Current Address Read or a Random Address Read. The master does acknowledge the data byte output in this case, and the memory continues to output the next byte in sequence. To terminate the stream of bytes, the master must not acknowledge the last byte output, and must generate a STOP condition. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’ and the memory continues to output data from address 00h (at the start of the memory block). Acknowledge in Read Mode In all read modes, the memory waits, after each byte read, for an acknowledgment during the 9th bit time. If the master does not pull the SDA line low during this time, the memory terminates the data transfer and switches to its standby state. USE WITHIN A DRAM DIMM In the application, the M34C02 is soldered directly in the printed circuit module. The 3 Chip Enable inputs (pins 1, 2 and 3) are connected to pins 165, 166 and 167, respectively, of the 168-pin DRAM DIMM module. They are wired at VCC or VSS through the DIMM socket (see Table 5). The SCL and SDA lines (pins 6 and 5) are connected respectively to pins 83 and 82 of the memory module. The pull-up resistors needed for normal behavior of the I2C bus are connected on the I2C bus of the mother-board (as shown in Figure 10). The Write Control input of the M34C02 (WC on pin 7) can be left unconnected. However, connecting it to VSS is recommended, to maintain full read and write access to the top half of the memory. Programming the M34C02 When the M34C02 is delivered, full read and write access is given to the whole memory array. It is recommended that the first step is to use the test equipment to write the module information (such as its access speed, its size, its organization) to the first half of the memory, starting from the first memory location. When the data has been validated, the test equipment can send a Write command to the Protection Register, using the device select code ’01100000b’ followed by an address and data byte (made up of Don’t Care values) as shown in Figure 8. The first 128 bytes of the memory area are then write-protected, and the M34C02 will no longer respond to the specific device select code ’0110000xb’. It is not possible to reverse this sequence. Table 5. 168 Pin DRAM DIMM Connections DIMM Position E2 (pin 167) E1 (pin 166) E0 (pin 165) 0 VSS VSS VSS 1 VSS VSS VCC 2 VSS VCC VSS 3 VSS VCC VCC 4 VCC VSS VSS 5 VCC VSS VCC 6 VCC VCC VSS 7 VCC VCC VCC |
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