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LM3S1968-IRN50-A1T Datasheet(PDF) 6 Page - List of Unclassifed Manufacturers

Part # LM3S1968-IRN50-A1T
Description  Microcontroller
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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LM3S1968-IRN50-A1T Datasheet(HTML) 6 Page - List of Unclassifed Manufacturers

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13.5
Register Descriptions .............................................................................................................. 300
14
Synchronous Serial Interface (SSI) ................................................................................ 334
14.1
Block Diagram ........................................................................................................................ 334
14.2
Functional Description ............................................................................................................. 334
14.2.1 Bit Rate Generation ................................................................................................................. 335
14.2.2 FIFO Operation ....................................................................................................................... 335
14.2.3 Interrupts ................................................................................................................................ 335
14.2.4 Frame Formats ....................................................................................................................... 336
14.3
Initialization and Configuration ................................................................................................. 343
14.4
Register Map .......................................................................................................................... 344
14.5
Register Descriptions .............................................................................................................. 345
15
Inter-Integrated Circuit (I
2C) Interface ............................................................................ 371
15.1
Block Diagram ........................................................................................................................ 371
15.2
Functional Description ............................................................................................................. 371
15.2.1 I
2C Bus Functional Overview .................................................................................................... 372
15.2.2 Available Speed Modes ........................................................................................................... 374
15.2.3 Interrupts ................................................................................................................................ 375
15.2.4 Loopback Operation ................................................................................................................ 375
15.2.5 Command Sequence Flow Charts ............................................................................................ 375
15.3
Initialization and Configuration ................................................................................................. 382
15.4
I
2C Register Map ..................................................................................................................... 383
15.5
Register Descriptions (I
2C Master) ........................................................................................... 384
15.6
Register Descriptions (I2C Slave) ............................................................................................. 397
16
Analog Comparators ....................................................................................................... 406
16.1
Block Diagram ........................................................................................................................ 407
16.2
Functional Description ............................................................................................................. 407
16.2.1 Internal Reference Programming .............................................................................................. 409
16.3
Initialization and Configuration ................................................................................................. 410
16.4
Register Map .......................................................................................................................... 410
16.5
Register Descriptions .............................................................................................................. 411
17
Pulse Width Modulator (PWM) ........................................................................................ 419
17.1
Block Diagram ........................................................................................................................ 419
17.2
Functional Description ............................................................................................................. 419
17.2.1 PWM Timer ............................................................................................................................. 419
17.2.2 PWM Comparators .................................................................................................................. 420
17.2.3 PWM Signal Generator ............................................................................................................ 421
17.2.4 Dead-Band Generator ............................................................................................................. 422
17.2.5 Interrupt/ADC-Trigger Selector ................................................................................................. 422
17.2.6 Synchronization Methods ......................................................................................................... 422
17.2.7 Fault Conditions ...................................................................................................................... 423
17.2.8 Output Control Block ............................................................................................................... 423
17.3
Initialization and Configuration ................................................................................................. 423
17.4
Register Map .......................................................................................................................... 424
17.5
Register Descriptions .............................................................................................................. 426
18
Quadrature Encoder Interface (QEI) ............................................................................... 455
18.1
Block Diagram ........................................................................................................................ 455
18.2
Functional Description ............................................................................................................. 456
September 02, 2007
6
Preliminary
Table of Contents


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