K4X56163PI - L(F)E/G

- 14 -

Mobile DDR SDRAM

October 2007

12. DC CHARACTERISTICS

°C)

NOTE :

1) It has +/- 5

°C tolerance.

2) DPD(Deep Power Down) function is an optional feature, and it will be enabled upon request.

Please contact Samsung for more information.

3) IDD specifications are tested after the device is properly intialized.

4) Input slew rate is 1V/ns.

≤ 0.1 * VDDQ ;

≥ 0.9 * VDDQ ;

STABLE is defined as inputs stable at a HIGH or LOW level ;

SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles ;

- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.

Parameter

Symbol

Test Condition

DDR333 DDR266 Unit Note

Operating Current

(One Bank Active)

IDD0

tRC=tRCmin; tCK=tCKmin; CKE is HIGH; CS is HIGH between valid com-

mands; address inputs are SWITCHING; data bus inputs are STABLE

50

45

mA

Precharge Standby Current

in power-down mode

IDD2P

all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin;

address and control inputs are SWITCHING; data bus inputs are STABLE

0.3

mA

IDD2PS

all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;

address and control inputs are SWITCHING; data bus inputs are STABLE

0.3

Precharge Standby Current

in non power-down mode

IDD2N

all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin;

address and control inputs are SWITCHING; data bus inputs are STABLE

15

12

mA

IDD2NS

all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;

address and control inputs are SWITCHING; data bus inputs are STABLE

8

8

Active Standby Current

in power-down mode

IDD3P

one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin;

address and control inputs are SWITCHING; data bus inputs are STABLE

5

mA

IDD3PS

one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;

address and control inputs are SWITCHING; data bus inputs are STABLE

2

Active Standby Current

in non power-down mode

(One Bank Active)

IDD3N

one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin;

address and control inputs are SWITCHING; data bus inputs are STABLE

25

25

mA

IDD3NS

one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;

address and control inputs are SWITCHING; data bus inputs are STABLE

20

20

Operating Current

(Burst Mode)

IDD4R

one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts;

address inputs are SWITCHING; 50% data change each burst transfer

110

95

mA

IDD4W

one bank active; BL = 4; tCK = tCKmin ; continuous write bursts;

address inputs are SWITCHING; 50% data change each burst transfer

90

75

Refresh Current

IDD5

tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is HIGH;

address and control inputs are SWITCHING; data bus inputs are STABLE

100

85

mA

Self Refresh Current

IDD6

CKE is LOW; t CK = t CKmin ;

Extended Mode Register set to all 0’s;

address and control inputs are STABLE;

data bus inputs are STABLE

Parameter

85

°C

- E

Full Array

200

450

uA

1/2 Array

160

300

1/4 Array

140

250

- G

Full Array

150

300

1/2 Array

135

250

1/4 Array

130

225

Deep Power Down Current

IDD8

Deep Power Down Mode Current

10

uA

2