3/22

M29F200BT, M29F200BB

The blocks in the memory are asymmetrically ar-

ranged, see Tables 3A and 3B, Block Addresses.

The first or last 64 Kbytes have been divided into

four additional blocks. The 16 Kbyte Boot Block

can be used for small initialization code to start the

microprocessor, the two 8 Kbyte Parameter

Blocks can be used for parameter storage and the

remaining 32K is a small Main Block where the ap-

plication may be stored.

Chip Enable, Output Enable and Write Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, often without additional logic.

The memory is offered in TSOP48 (12 x 20mm)

and SO44 packages. Access times of 45ns, 55ns,

70ns and 90ns are available. The memory is sup-

plied with all the bits erased (set to ’1’).

SIGNAL DESCRIPTIONS

See Figure 1, Logic Diagram, and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A16). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation. During Bus

Write operations they represent the commands

sent to the Command Interface of the internal state

machine.

Data Inputs/Outputs (DQ8-DQ14). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation when BYTE

are not used and are high impedance. During Bus

Write operations the Command Register does not

use these bits. When reading the Status Register

these bits should be ignored.

Data Input/Output or Address Input (DQ15A-1).

Data Input/Output pin (as DQ8-DQ14). When

pin; DQ15A–1 Low will select the LSB of the Word

on the other addresses, DQ15A–1 High will select

the MSB. Throughout the text consider references

to the Data Input/Output to include this pin when

BYTE is High and references to the Address In-

puts to include this pin when BYTE is Low except

when stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write op-

erations to be performed. When Chip Enable is

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

mand Interface.

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

Symbol

Parameter

Value

Unit

Ambient Operating Temperature (Temperature Range Option 1)

0 to 70

°C

Ambient Operating Temperature (Temperature Range Option 6)

–40 to 85

°C

Ambient Operating Temperature (Temperature Range Option 3)

–40 to 125

°C

Temperature Under Bias

–50 to 125

°C

Storage Temperature

–65 to 150

°C

(2)

Input or Output Voltage

–0.6 to 6

V

Supply Voltage

–0.6 to 6

V

Identification Voltage

–0.6 to 13.5

V