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ADS61B23IRHBT Datasheet(PDF) 10 Page - Texas Instruments |
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ADS61B23IRHBT Datasheet(HTML) 10 Page - Texas Instruments |
10 / 51 page www.ti.com ADS61B23 SLAS582 – FEBRUARY 2008 Table 1. Timing Characteristics at Lower Sampling Frequencies (1)(2) tsu DATA SETUP TIME, ns th DATA HOLD TIME, ns tPDI CLOCK PROPAGATION DELAY, ns Fs, MSPS MIN TYP MAX MIN TYP MAX MIN TYP MAX CMOS INTERFACE, DRVDD = 2.5 V to 3.6 V 65 5.1 6.6 3.8 5 5 6.5 7.9 40 6.5 8 5.3 6.5 20 11.3 12.8 10 11.2 10 23 25 21 23 DDR LVDS INTERFACE, DRVDD = 3.0 V to 3.6 V 65 5.4 6 0.7 1.7 4.3 5.8 7.3 40 10.2 10.8 4.3 5.8 7.3 20 22 23 4.5 6.5 8.5 10 47 48 4.5 6.5 8.5 (1) Timing parameters are specified by design and characterization and not tested in production. (2) Timings are specified with default output buffer drive strength and CL= 5 pF. 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B23 |
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