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M28010-10BA6T Datasheet(PDF) 7 Page - STMicroelectronics |
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M28010-10BA6T Datasheet(HTML) 7 Page - STMicroelectronics |
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7 / 23 page  7/23 M28010 memory from inadvertent write cycles that may occur during periods of instability (uncontrolled bus conditions when excessive noise is detected, or when power supply levels are outside their specified values). By default, the device is shipped in the “unprotected” state: the memory contents can be freely changed by the user. Once the Software Data Protection Mode is enabled, all write commands are ignored, and have no effect on the memory contents. The device remains in this mode until a valid Software Data Protection disable sequence is received. The device reverts to its “unprotected” state. The status of the Software Data Protection (enabled or disabled) is represented by a non- volatile latch, and is remembered across periods of the power being off. The Software Data Protection Enable command consists of the writing of three specific data bytes to three specific memory locations (each location being on a different page), as shown in Figure 4. Similarly, to disable the Software Data Protection, the user has to write specific data bytes into six different locations, as shown in Figure 5. This complex series of operations protects against the chance of inadvertent enabling or disabling of the Software Data Protection mechanism. When SDP is enabled, the memory array can still have data written to it, but the sequence is more complex (and hence better protected from inadvertent use). The sequence is as shown in Figure 5. This consists of an unlock key, to enable the write action, at the end of which the SDP continues to be enabled. This allows the SDP to be enabled, and data to be written, within a single Write cycle (tWC). Figure 6. Software Chip Erase Algorithm Wait for write completion (tQ5HQ5X) AI02236C Write AAh in Address 5555h Write 55h in Address 2AAAh Write 80h in Address 5555h Whole Array has been Set to FFh Write AAh in Address 5555h Write 55h in Address 2AAAh Write 10h in Address 5555h Page Write Timing Time Out (tWLQ5H) Figure 7. Status Bit Assignment Figure 8. Software Data Protection Status Read Algorithm AI02486B DP TB PLTS X X X PWA SDP DP TB PLTS X PWA SDP DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 = Data Polling = Toggle Bit = Page Load Timer Status = undefined = Page Write Abort = Software Data Protection AI02237B Write AAh in Address 5555h Write 55h in Address 2AAAh Write 20h in Address 5555h Normal User Mode Read SDP on DQ0 Write xxh in Address xxxxh Page Write Timing |
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