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M295V200T-55N1TR Datasheet(PDF) 5 Page - STMicroelectronics |
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M295V200T-55N1TR Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 33 page Command Interface Instructions, made up of commands written in cy- cles, can be given to the Program/Erase Controller through a Command Interface (C.I.). For added data protection, program or erase execution starts after 4 or 6 cycles. The first, second, fourth and fifth cycles are used to input Coded cycles to the C.I. This Coded sequence is the same for all Pro- gram/Erase Controller instructions. The ’Com- mand’ itself and its confirmation, when applicable, are given on the third, fourth or sixth cycles. Any incorrect command or any improper command se- quence will reset the device to Read Array mode. Instructions Seven instructions are defined to perform Read Array, Auto Select (to read the ElectronicSignature or Block Protection Status), Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume. The internal P/E.C. automatically handles all tim- ing and verification of the Program and Erase operations. The Status Register Data Polling, Tog- gle, Error bits and the RB output may be read at any time, during programming or erase, to monitor the progress of the operation. Instructions are composed of up to six cycles. The first two cycles input a Coded sequence to the Command Interfacewhich is common to all instruc- tions (see Table 8). The third cycle inputs the instruction set-up command. Subsequent cycles output the addressed data, Electronic Signature or Block Protection Status for Read operations. In order to give additional data protection, the instruc- tions for Program and Block or Chip Erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be programmed. For an Erase instruction (Block or Chip), the fourth and fifth cycles input a further Coded sequence before the Erase confirm command on the sixth cycle. Erasure of a memory block may be suspended,in orderto read data from another block or to program data in another block, and then resumed. When power is first applied or if VCC falls below VLKO, the command interface is reset to Read Array. SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A16). The address inputs for the memory array are latched during a write opera- tion on the falling edge of Chip Enable E or Write Enable W. In Word-wide organisation the address lines are A0-A16, in Byte-wide organisation DQ15A–1 acts as an additional LSB address line. When A9 is raised to VID, either a Read Electronic Signature Manufacturer or Device Code, Block Protection Status or a Write Block Protection or Block Unprotection is enabled depending on the combination of levels on A0, A1, A6, A12 and A15. Data Input/Outputs (DQ0-DQ7). T hes e I n- puts/Outputsare used in the Byte-wide and Word- wide organisations. The input is data to be programmed in the memory array or a command to be written to the C.I. Both are latched on the rising edge of Chip Enable E or Write Enable W. The output is data from the Memory Array, the Electronic Signature Manufacturer or Device codes, the Block Protection Status or the Status register Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5 or the Erase Timer bit DQ3. Outputs are valid when Chip Enable E and Output Enable G are active. The output is high impedance when the chip is deselected or the outputsare disabled and when RP is at a Low level. Data Input/Outputs (DQ8-DQ14 and DQ15A–1). These Inputs/Outputs are additionally used in the Word-wide organisation. When BYTEis High DQ8- DQ14 and DQ15A–1 act as the MSB of the Data Input or Output, functioning as described for DQ0- DQ7 above, and DQ8-DQ15 are ’don’t care’ for command inputs or status outputs. When BYTE is Low, DQ8-DQ14 are high impedance, DQ15A–1 is the Address A–1 input. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. E High deselectsthe memory and reduces the power consumption to the standby level. E can also be used to control writing to the command register and to the memory array, while W remains at a low level. The Chip Enable must be forced to VID during the Block Unprotection opera- tion. Output Enable (G). The Output Enable gates the outputs through the data buffers during a read operation. When G is High the outputs are High impedance. G must be forced to VID level during Block Protection and Unprotection operations. Write Enable (W). This input controls writing to the Command Registerand Addressand Data latches. Byte/Word Organization Select (BYTE) . The BYTE input selects the output configuration for the device: Byte-wide (x8) mode or Word-wide (x16) mode. When BYTE is Low, the Byte-wide mode is selected and the data is read and programmed on DQ0-DQ7. In this mode, DQ8-DQ14 are at high impedance and DQ15A–1 is the LSB address. When BYTE is High, the Word-wide mode is se- lected and the data is read and programmed on DQ0-DQ15. 5/33 M29F200T, M29F200B |
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