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CD74HCT93E Datasheet(PDF) 1 Page - Texas Instruments |
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CD74HCT93E Datasheet(HTML) 1 Page - Texas Instruments |
1 / 13 page 1 Data sheet acquired from Harris Semiconductor SCHS138C Features • Can Be Configured to Divide By 2, 8, and 16 • Asynchronous Master Reset • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Pinout CD74HC93 (PDIP, SOIC) CD74HCT93 (PDIP) TOP VIEW Description The CD74HC93 and CD74HCT93 are high-speed silicon-gate CMOS devices and are pin-compatible with low power Schottky TTL (LSTTL). These 4-bit binary ripple counters consist of four master-slave flip-flops internally connected to provide a divide-by-two section and a divide- by-eight section. Each section has a separate clock input (CP0 and CP1) to initiate state changes of the counter on the HIGH to LOW clock transition. State changes of the Qn outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. A gated AND asynchronous master reset (MR1 and MR2 is provided which overrides both clocks and resets (clears) all flip-flops. Because the output from the divide by two section is not internally connected to the succeeding stages, the device may be operated in various counting modes. In a 4-bit ripple counter the output Q0 must be connected externally to input CP1. The input count pulses are applied to clock input CP0. Simultaneous frequency divisions of 2, 4, 8, and 16 are performed at the Q0,Q1,Q2, and Q3 outputs as shown in the function table. As a 3-bit ripple counter the input count pulses are applied to input CP1. Simultaneous frequency divisions of 2, 4, and 8 are available at the Q1,Q2,Q3 outputs. Independent use of the first flip- flop is available if the reset function coincides with the reset of the 3-bit ripple-through counter. CP1 MR1 MR2 NC VCC NC NC CPO NC Q0 Q3 GND Q1 Q2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE CD74HC93E -55 to 125 14 Ld PDIP CD74HC93M -55 to 125 14 Ld SOIC CD74HC93MT -55 to 125 14 Ld SOIC CD74HC93M96 -55 to 125 14 Ld SOIC CD74HCT93E -55 to 125 14 Ld PDIP NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. August 1997 - Revised September 2003 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated CD74HC93, CD74HCT93 High-Speed CMOS Logic 4-Bit Binary Ripple Counter [ /Title (CD74 HC93, CD74 HCT93 ) /Sub- ject (High Speed CMOS Logic 4-Bit Binary Ripple Counte r) |
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