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ADSP-BF538BBCZ-5F4 Datasheet(PDF) 7 Page - Analog Devices |
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ADSP-BF538BBCZ-5F4 Datasheet(HTML) 7 Page - Analog Devices |
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7 / 56 page  ADSP-BF538/ADSP-BF538F Rev. A | Page 7 of 56 | January 2008 event service routines to be active simultaneously. Prioritization ensures that servicing of a higher priority event takes prece- dence over servicing of a lower priority event. The controller provides support for five different types of events: • Emulation – An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface. • Reset – This event resets the processor. • Nonmaskable interrupt (NMI) – The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shut- down of the system. • Exceptions – Events that occur synchronously to program flow (the exception is taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions. • Interrupts – Events that occur asynchronously to program flow. They are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction. Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processors is saved on the supervisor stack. The ADSP-BF538/ADSP-BF538F processors’ event controllers consist of two stages, the core event controller (CEC), and the system interrupt controllers (SIC). The core event controller works with the system interrupt controllers to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into one of the SICs, and are then routed directly into the general-purpose interrupts of the CEC. Core Event Controller (CEC) The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest priority inter- rupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the processor. Table 2 describes the inputs to the CEC, identifies their names in the event vector table (EVT), and lists their priorities. Table 2. Core Event Controller (CEC) Priority (0 is Highest) Event Class EVT Entry 0Emulation/Test Control EMU 1 Reset RST 2 Nonmaskable Interrupt NMI 3Exception EVX 4 Reserved — 5 Hardware Error IVHW 6Core Timer IVTMR 7 General Interrupt 7 IVG7 8 General Interrupt 8 IVG8 9 General Interrupt 9 IVG9 10 General Interrupt 10 IVG10 11 General Interrupt 11 IVG11 12 General Interrupt 12 IVG12 13 General Interrupt 13 IVG13 14 General Interrupt 14 IVG14 15 General Interrupt 15 IVG15 |
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