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M28010-25NA1T Datasheet(PDF) 2 Page - STMicroelectronics |
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M28010-25NA1T Datasheet(HTML) 2 Page - STMicroelectronics |
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2 / 23 page  M28010 2/23 Figure 2A. DIP Connections Note: 1. DU = Do Not Use Figure 2B. PLCC Connections Note: 1. DU = Do Not Use A1 A0 DQ0 A7 A4 A3 A2 A6 A5 A13 A10 A8 A9 DQ7 A14 A11 G E DQ5 DQ1 DQ2 DQ3 VSS DQ4 DQ6 A12 DU VCC AI02222 M28010 8 1 15 16 4 5 6 7 9 10 11 12 13 14 32 31 30 27 26 25 24 23 22 21 20 19 18 17 A15 DU W A16 2 3 29 28 AI02223 A8 A10 17 A0 A7 DQ0 A6 A3 A2 A1 A5 A4 9 A9 1 A11 A14 DQ7 32 M28010 A13 G E 25 Figure 2C. TSOP Connections Note: 1. DU = Do Not Use A2 A1 A0 A6 A3 A5 A4 A9 A11 DQ7 A8 G E DQ5 DQ0 DQ1 DQ3 DQ4 DQ6 A13 W A15 A7 A14 VCC A12 AI02224 M28010 8 1 9 16 17 24 25 32 VSS A10 DQ2 DU A16 DU The device has been designed to offer a flexible microcontroller interface, featuring both hardware and software hand-shaking, with Data Polling and Toggle Bit. The device supports a 128 byte Page Write operation. Software Data Protection (SDP) is also supported, using the standard JEDEC algorithm. The M28010 is designed for applications requiring as much as 100,000 write cycles and ten years of data retention. The organization of the data in a 4 byte (32-bit) “word” format leads to significant savings in power consumption. Once a byte has been read, subsequent byte read cycles from the same “word” (with addresses differing only in the two least significant bits) are fetched from the previously loaded Read Buffer, not from the memory array. As a result, the power consumption for these subsequent read cycles is much lower than the power consumption for the first cycle. By careful design of the memory access patterns, a 50% reduction in the power consumption is possible. SIGNAL DESCRIPTION The external connections to the device are summarized in Table 1, and their use in Table 3. Addresses (A0-A16). The address inputs are used to select one byte from the memory array during a read or write operation. Data In/Out (DQ0-DQ7). The contents of the data byte are written to, or read from, the memory array through the Data I/O pins. Chip Enable (E). The chip enable input must be held low to enable read and write operations. When Chip Enable is high, power consumption is reduced. Output Enable (G). The Output Enable input controls the data output buffers, and is used to initiate read operations. |
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Similar Description - M28010-25NA1T |
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