ICL7135C, TLC7135C

4 1/2DIGIT PRECISION

ANALOGTODIGITAL CONVERTERS

SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003

7

POST OFFICE BOX 655303

DESCRIPTION OF ANALOG CIRCUITS

Input Signal Range

The common mode range of the input amplifier extends from 1 V above the negative supply to 1 V below the

positive supply. Within this range, the common-mode rejection ratio (CMRR) is typically 86 dB. Both differential

and common-mode voltages cause the integrator output to swing. Therefore, care must be exercised to ensure

that the integrator output does not become saturated.

Analog Common

Analog common (ANLG COMMON) is connected to the internal IN− during the auto-zero, deintegrate, and zero

integrator phases. When IN − is connected to a voltage that is different from analog common during the signal

integrate phase, the resulting common-mode voltage is rejected by the amplifier. However, in most applications,

IN− is set at a known fixed voltage (i.e., power supply common for instance). In this application, analog common

should be tied to the same point, thus removing the common-mode voltage from the converter. Removing the

common-mode voltage in this manner slightly increases conversion accuracy.

Reference

The reference voltage is positive with respect to analog common. The accuracy of the conversion result is

dependent upon the quality of the reference. Therefore, to obtain a high accuracy conversion, a high quality

reference should be used.

DESCRIPTION OF DIGITAL CIRCUITS

RUN/HOLD Input

When RUN/HOLD is high or open, the device continuously performs measurement cycles every 40,002 clock

pulses. When this input is taken low, the integrated circuit continues to perform the ongoing measurement cycle

and then hold the conversion reading for as long as the terminal is held low. When the terminal is held low after

completion of a measurement cycle, a short positive pulse (greater than 300 ns) initiates a new measurement

cycle. When this positive pulse occurs before the completion of a measurement cycle, it will not be recognized.

The first STROBE pulse, which occurs 101 counts after the end of a measurement cycle, is an indication of the

completion of a measurement cycle. Thus, the positive pulse could be used to trigger the start of a new

measurement after the first STROBE pulse.

STROBE Input

Negative going pulses from this input transfer the BCD conversion data to external latches, UARTs, or

microprocessors. At the end of the measurement cycle, STROBE goes high and remains high for 201 counts.

The most significant digit (MSD) BCD bits are placed on the BCD terminals. After the first 101 counts, halfway

through the duration of output D1−D5 going high, the STROBE terminal goes low for 1/2 clock pulse width. The

placement of the STROBE pulse at the midpoint of the D5 high pulse allows the information to be latched into

an external device on either a low-level or an edge. Such placement of the STROBE pulse also ensures that

the BCD bits for the second MSD are not yet competing for the BCD lines and latching of the correct bits is

ensured. The above process is repeated for the second MSD and the D4 output. Similarly, the process is

repeated through the least significant digit (LSD). Subsequently, inputs D5 through D1 and the BCD lines

continue scanning without the inclusion of STROBE pulses. This subsequent continuous scanning causes the

conversion results to be continuously displayed. Such subsequent scanning does not occur when an over-range

condition occurs.