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Board thickness

62 mils(0.15748cm)

Boardsize

3.2in.x3.2in.

Boardmaterial

FR4

Coppertrace/heatsink

1 oz

Exposedpadmounting

63/67tin/lead(Sn/Pb)solder

Heatsink Area

1ozCopper

P

=

D(Max)

T

T

R

-

J(Max)

A

JA (System)

q

(5)

P

=(V

V

)

I

+V

I

-

D(total)

IN

OUT

OUT

IN

Q

´

´

(6)

P

=(V

V

)

I

-

D(total)

IN

OUT

OUT

´

(7)

P

=

D(Max)

T

T

R

-

J(Max)

A

JA (System)

q

=

=1.4W

125

-

°

C

°

°

C

C/W

55

50

(8)

P

=(V

V

)

I

-

D(total)

IN

OUT

OUT

´

=(5

3.3)

0.8=1.36W

-

´

(9)

TPS752xxQ

TPS754xxQ

SLVS242C – MARCH 2000 – REVISED OCTOBER 2007

Figure 29 is an example of a thermally-enhanced PWB layout for use with the new PWP package. This board

configuration was used in the thermal experiments that generated the power ratings shown in Figure 27 and

for this assembly is illustrated in Figure 27 as a function of heatsink area. A family of curves is included to

illustrate the effect of airflow introduced into the system.

Figure 29. PWB Layout (Including Copper Heatsink Area) for Thermally-Enhanced PWP Package

power-dissipation limit for the component/PWB assembly, with the equation:

for calculating total internal power dissipation of the TPS75433QPWP is:

Because the quiescent current of the TPS75433QPWP is very low, the second term is negligible, further

simplifying the equation to:

maximum power-dissipation limit is:

dissipation is:

limit. When it does, one of two corrective actions should be made: either raise the power-dissipation limit by

increasing the airflow or the heat-sink area, or loweri the internal power dissipation of the regulator by reducing

the input voltage or the load current. In either case, the above calculations should be repeated with the new

system parameters.

Copyright © 2000–2007, Texas Instruments Incorporated

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