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STW81103ATR Datasheet(PDF) 48 Page - STMicroelectronics |
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STW81103ATR Datasheet(HTML) 48 Page - STMicroelectronics |
48 / 53 page Application diagram STW81103 48/53 Figure 37. Ping-pong architecture diagram Note: 1 See Section 8: Application information for further information on output matching topology. 2 EXT_PD, ADD2, ADD1 (and ADD0 when the I2C bus is selected) can be hard wired directly on the board. 3 Loop filter values are for FSTEP = 200 kHz. 4 For best performance VDD1_1 and VDD1_2 must be low noise supplies (20 μVRMS in 10 Hz-100 KHz BW). |
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