STW81103ATR datasheet(29/53 Pages) STMICROELECTRONICS

Part #	STW81103ATR

Description	Multi-band RF frequency synthesizer with integrated VCOs

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STW81103

I2C bus interface

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6.1.5

Single-byte write mode

Following a START condition, the master sends a device select code with the RW bit set to

0. The STW81103 sends an acknowledge and waits for the 1-byte internal sub-address that

provides access to the internal registers.

After receiving the sub-address internal byte, the STW81103 again responds with an

acknowledge. A single-byte write to sub-address 00H changes the FUNCTIONAL_MODE

register, a single-byte write with sub-address 04H changes the CONTROL register, and so

on.

6.1.6

Multi-byte write mode

The multi-byte write mode can start from any internal address. The master sends the data

bytes, and each one is acknowledged. The master terminates the transfer by generating a

STOP condition.

The sub-address decides the starting byte. For example, a multi-byte with sub-address 01H

and 2 DATA_IN bytes changes the B_COUNTER and A_COUNTER registers (01H,02H),

and a multi-byte with sub-address 00H and 6 DATA_IN bytes changes all the STW81103

registers.

6.1.7

Current byte address read mode

In the current byte address read mode, following a START condition, the master sends the

device address with the RW bit set to 1. Note that no sub-address is needed since there is

only one read register. The STW81103 acknowledges this and outputs the data byte. The

master does not acknowledge the received byte, and terminates the transfer with a STOP

condition.

Table 11.

Single-byte write mode

S

1100A2A1A0

0

ack

sub-address byte

ack

DATA IN

ack

P

Table 12.

Multi-byte write mode

S

1100A2A1A0 0 ack

sub-address byte

ack

DATA IN

ack

…….

DATA IN

ack

P

Table 13.

Current byte address read mode

S

1100A2A1A0

1

ack

DATA OUT

No ack

P

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