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82544EI Datasheet(PDF) 13 Page - Intel Corporation |
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82544EI Datasheet(HTML) 13 Page - Intel Corporation |
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13 / 52 page  82544EI Gigabit Ethernet Controller Networking Silicon Datasheet Datasheet 9 TRDY# STS Target Ready. TRDY# indicates the ability of the 82544EI controller (as a selected device) to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed on any clock in which both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that valid data is present on AD[63:0]. During a write, it indicates the target is ready to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. The 82544EI device drives IRDY# when acting as a slave and samples it when acting as a master. STOP# STS Stop. STOP# indicates the current target is requesting the master to stop the current transaction. As a slave, the 82544EI controller drives STOP# to request the bus master to stop the transaction. As a master, the 82544EI controller receives STOP# from the slave and stops the current transaction. IDSEL I Initialization Device Select. IDSEL is used by the 82544EI device as a chip select during configuration read and write transactions. DEVSEL# STS Device Select. When being actively driven by the 82544EI controller, DEVSEL# indicates to the bus master that it has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected. VIO P VIO. VIO is a voltage reference for PCI interface (3.3 V or 5 V). It is used as the clamping voltage. NOTE: An external resistor is required between the voltage reference and the VIO balls.The targeted resistor value is 100 K Ω. Signal Name Type Name and Function |
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