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M28C16-150K6TR Datasheet(PDF) 6 Page - STMicroelectronics |
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M28C16-150K6TR Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 17 page M28C16B, M28C17B 6/17 Table 5. Chip Erase AC Characteristics1 (TA = 0 to 70 °C or -40 to 85 °C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V) Note: 1. Sampled only, not 100% tested. Symbol Parameter Test Condition Min. Max. Unit tELWL Chip Enable Low to Write Enable Low G = VCC + 7V 1 µs tWHEH Write Enable High to Chip Enable High G = VCC + 7V 0 ns tWLWH2 Write Enable Low to Write Enable High G = VCC + 7V 10 ms tGLWH Output Enable Low to Write Enable High G = VCC + 7V 1µs tWHRH Write Enable High to Write Enable Low G = VCC + 7V 3 ms Figure 7. Chip Erase AC Waveforms AI01484B E G W tWLWH2 tELWL tGLWH tWHRH tWHEH When SDP is enabled, the memory array can still have data written to it, but the sequence is more complex (and hence better protected from inad- vertent use). The sequence is as shown in Figure 4. This consists of an unlock key, to enable the write action, at the end of which the SDP continues to be enabled. This allows the SDP to be enabled, and data to be written, within a single Write cycle (tWC). Software Chip Erase The contents of the entire memory are erased (set to FFh) by holding Chip Enable (E) low, and hold- ing Output Enable (G) at VCC+7.0V. The chip is cleared when a 10 ms low pulse is applied to the Write Enable (W) signal (see Figure 7 and Table 5 for details). Status Bits The devices provide three status bits (DQ7, DQ6 and DQ5), for use during write operations. These allow the application to use the write time latency of the device for getting on with other work. These signals are available on the I/O port bits DQ7, DQ6 and DQ5 (but only during programming cycle, once a byte or more has been latched into the memory). Data Polling bit (DQ7). The internally timed write cycle starts after tWLQ5H (defined in Table 10A) has elapsed since the previous byte was latched in to the memory. The value of the DQ7 bit of this last byte, is used as a signal throughout this write op- eration: it is inverted while the internal write oper- ation is underway, and is inverted back to its original value once the operation is complete. Toggle bit (DQ6). The device offers another way for determining when the internal write cycle is completed. During the internal Erase/Write cycle, DQ6 toggles from ’0’ to ’1’ and ’1’ to ’0’ (the first read value being ’0’) on subsequent attempts to read any byte of the memory. When the internal write cycle is complete, the toggling is stopped, and the values read on DQ7-DQ0 are those of the addressed memory byte. This indicates that the device is again available for new Read and Write operations. Page Load Timer Status bit (DQ5). An internal timer is used to measure the period between suc- |
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