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MSU2052 Datasheet(PDF) 6 Page - Mosel Vitelic, Corp |
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MSU2052 Datasheet(HTML) 6 Page - Mosel Vitelic, Corp |
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6 / 21 page  6 Rev. 1.0 February 1998 MOSEL VITELIC MSU2052/U2032 Power Down Mode It saves the RAM content, stops the clock generator and disables every other blocks' function until the coming hardware reset. To save even more power consumption, user's software program can invoke this mode. The SFRs and the on-chip data RAM retain their values during this mode, but the porcessor stops executing instructions. In Power-Down mode (PD=1) the oscillator is frozen. -An instruction that sets flag (PCON.1) causes that to be the last instruction executed before going into the Power Down Mode. -In the Power Down Mode, the on-chip oscillator is stopped. With the clock frozen, all functions are stopped, but the on-chip RAM and Special Function Registers are held. -Reset redefines all the SFRs, but does not change the on-chip RAM. -There are two ways to terminate the Power Down Mode. 1) By hardware reset All SFR and PC value will be cleared to reset value. 2) One of CLK, DATA, PORT 2.0-2.7 transition to low (falling edge trigger) After the program wakes up, the PC value will be 0023h (if enable IE register) and execute interrupt service routine and then returns to PC+1 address after the program wakes up. -Care must be taken, however, to ensure that VCC is not reduced before the Power Down Mode is invoked, and that VCC is restored to its normal operating level before the Power Down Mode is terminated. -The hardware reset must be held active long enough to allow the oscillator to restart and stabilize. General of above User should fix the attention on using wake up from port 2: -The user should write the power down or idle mode flag value to one RAM address before write PCON to distinguish waking up from power down mode or idle mode. -After idle mode or power down mode wakes up, the interrupt service routine will be executed first and then executes PC+1 address if the IE register is enabled before entering power down mode or idle mode. The interrupt service routine will not be executed but CPU executes PC+1 address program if disable IE register. -After wake up power down or idle mode the IDF flag will be set by hardware. The IDF flag be cleared at the ISR execution time. If IE register is disable, the IDF flag will not be cleared when power down or idle mode wakes up. Mode Program memory ALE #PSEN Port 0 Port 1 Port 2 Port 3 Idle Idle Power Down Power Down Internal External Internal External 1 1 0 0 1 1 0 0 Data Float Data Float Data Data Data Data Data Address Data Data Data Data Data Data The state of pins during Idle and Power-Down Mode Symbol Vdd - Vss VIN VOUT T (Operating) T (Storage) Name DC supply Voltage Input voltage output voltage Operating Temperature Storage Temperature Rating -0.5 ~ +5.0 -0.5 ~ +7.0 Vss-0.3 ~ Vdd +0.3 Vss ~ Vdd 0 ~ +70 -55 ~ +125 Unit V V V Absolute Maximal Rating * Note: Operation beyond Absolute Maximal Rating can adversely affect device reliability. °C °C Remark U20x1L U20x1S,U20x1C |
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Similar Description - MSU2052 |
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