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EM6112K800TPA-55F Datasheet(PDF) 5 Page - Eorex Corporation

Part # EM6112K800TPA-55F
Description  512Kx8 LP SRAM
Download  13 Pages
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Manufacturer  EOREX [Eorex Corporation]
Direct Link  http://www.eorex.com
Logo EOREX - Eorex Corporation

EM6112K800TPA-55F Datasheet(HTML) 5 Page - Eorex Corporation

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512Kx8 LP SRAM EM6112K800V Series
5
DCC-SR-041005-A
CAPACITANCE (TA = 25°C , f = 1.0MHz)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Input Capacitance
CIN
-
6
pF
Input/Output Capacitance
CI/O
-
8
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0.2V to VCC - 0.2V
Input Rise and Fall Times
3ns
Input and Output Timing Reference Levels
1.5V
Output Load
CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
READ CYCLE
-45
-55
70
PARAMETER
SYM.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
UNIT
Read Cycle Time
tRC
45
-
55
-
70
-
ns
Address Access Time
tAA
-
45
-
55
-
70
ns
Chip Enable Access Time
tACE
-
45
-
55
-
70
ns
Output Enable Access Time
tOE
-
25
-
30
-
35
ns
Chip Enable to Output in Low-Z
tCLZ*
10
-
10
-
10
-
ns
Output Enable to Output in Low-Z
tOLZ*
5
-
5
-
5
-
ns
Chip Disable to Output in High-Z
tCHZ*
-
15
-
20
-
25
ns
Output Disable to Output in High-Z
tOHZ*
-
15
-
20
-
25
ns
Output Hold from Address Change
tOH
10
-
10
-
10
-
ns
WRITE CYCLE
-45
-55
70
PARAMETER
SYM.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
UNIT
Write Cycle Time
tWC
45
-
55
-
70
-
ns
Address Valid to End of Write
tAW
40
-
50
-
60
-
ns
Chip Enable to End of Write
tCW
40
-
50
-
60
-
ns
Address Set-up Time
tAS
0
-
0
-
0
-
ns
Write Pulse Width
tWP
35
-
45
-
55
-
ns
Write Recovery Time
twr
0
-
0
-
0
-
ns
Data to Write Time Overlap
tDW
20
-
25
-
30
-
ns
Data Hold from End of Write Time
tDH
0
-
0
-
0
-
ns
Output Active from End of Write
tOW*
5
-
5
-
5
-
ns
Write to Output in High-Z
tWHZ*
-
15
-
20
-
25
ns
*These parameters are guaranteed by device characterization, but not production tested.


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