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DESCRIPTION

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GND

GND

ENA

A1Y

A2Y

A3Y

A4Y

ENB

B1Y

B2Y

B3Y

B4Y

GND

GND

C1Y

C2Y

C3Y

C4Y

ENC

D1Y

D2Y

D3Y

D4Y

END

GND

GND

A1A

A1B

A2A

A2B

A3A

A3B

A4A

A4B

B1A

B1B

B2A

B2B

B3A

B3B

B4A

B4B

C1A

C1B

C2A

C2B

C3A

C3B

C4A

C4B

D1A

D1B

D2A

D2B

D3A

D3B

D4A

D4B

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2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1A

1B

2A

2B

3A

3B

4A

4B

EN1,2

1Y

2Y

GND

3Y

4Y

EN3,4

’LVDS390, ’LVDT390

D OR PW PACKAGE

(TOP VIEW)

’LVDS386, ’LVDT386

DGG PACKAGE

(TOP VIEW)

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38

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GND

ENA

A1Y

A2Y

ENB

B1Y

B2Y

DGND

DGND

C1Y

C2Y

ENC

D1Y

D2Y

END

GND

A1A

A1B

A2A

A2B

AGND

B1A

B1B

B2A

B2B

AGND

C1A

C1B

C2A

C2B

AGND

D1A

D1B

D2A

D2B

’LVDS388A, ’LVDT388A

DBT PACKAGE

(TOP VIEW)

and GND description.

SN65LVDS386/388A/390,, SN65LVDT386/388A/390

SN75LVDS386/388A/390, SN75LVDT386/388A/390

SLLS394H – SEPTEMBER 1999 – REVISED MAY 2007

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

• Four- ('390), Eight- ('388A), or Sixteen- ('386)

Line Receivers Meet or Exceed the

Requirements of ANSI TIA/EIA-644 Standard

• Integrated 110-Ω Line Termination Resistors

on LVDT Products

200 Mbps (See Table 1)

• SN65 Version's Bus-Terminal ESD Exceeds

15 kV

• Operates From a Single 3.3-V Supply

• Typical Propagation Delay Time of 2.6 ns

• Output Skew 100 ps (Typ) Part-To-Part Skew

Is Less Than 1 ns

• LVTTL Levels Are 5-V Tolerant

• Open-Circuit Fail Safe

• Flow-Through Pinout

• Packaged in Thin Shrink Small-Outline

Package With 20-mil Terminal Pitch

This family of four-, eight-, or sixteen-, differential line

receivers

(with

optional

integrated

termination)

implements

the

electrical

characteristics

of

low-voltage

differential

signaling

(LVDS).

This

signaling technique lowers the output voltage levels

of

5-V

differential

standard

levels

(such

as

EIA/TIA-422B) to reduce the power, increase the

switching speeds, and allow operation with a 3-V

supply rail. Any of the eight or sixteen differential

receivers provides a valid logical output state with a

±100-mV differential input voltage within the input

common-mode

voltage

range.

The

input

common-mode voltage range allows 1 V of ground

potential difference between two LVDS

nodes.

Additionally, the high-speed switching of LVDS

signals almost always requires the use of a line

impedance matching resistor at the receiving end of

the cable or transmission media. The LVDT products

Table 1. Maximum Recommeded Operating

eliminate this external resistor by integrating it with

Speeds

the receiver.

PART NUMBER

ALL BUFFERS ACTIVE

SN65LVDS386, SN75LVDS386

250 Mbps

SN65LVDS388A, SN75LVDS388A

200 Mbps

SN65LVDS390, SN75LVDS390

200 Mbps

(1)

Signaling Rate, 1/t, where t is the minimum unit interval and is

expressed in the units bits/s (bits per second)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 1999–2007, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.