eorex

EM482M3244VTA

Jul. 2006

www.eorex.com

AC Operating Test Characteristics (Continued)

-6

-7

Symbol

Parameter

Min.

Max.

Min.

Max.

Units

ACTIVE to ACTIVE Command

Period

(Note 6)

60

65

ns

ACTIVE to PRECHARGE

Command Period

(Note 6)

42

100k

45

100k

ns

PRECHARGE to ACTIVE

Command Period

(Note 6)

18

18

ns

ACTIVE to READ/WRITE Delay

Time

(Note 6)

18

18

ns

ACTIVE(one) to ACTIVE(another)

Command

(Note 6)

12

14

ns

READ/WRITE Command to

READ/WRITE Command

1

1

CLK

Date-in to PRECHARGE

Command

2

2

CLK

Date-in to BURST Stop Command

1

1

CLK

CL=3

3

3

Data-out

to High

Impedance from

PRECHARGE Command

CL=2

2

2

CLK

Refresh Time (4,096 cycle)

64

64

ms

Note 6: These parameters account for the number of clock cycles and depend on the operating frequency

of the clock, as follows:

The number of clock cycles = Specified value of timing/clock period (Count Fractions as a whole

number)

Recommended Power On and Initialization

The following power on and initialization sequence guarantees the device is preconditioned to each user’s

simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on

time)

After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the

precharge command.

To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be

held high during the initial pause period. Once all banks have been precharged, the Mode Register Set

Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR)

are also required, and these may be done before or after programming the Mode Register.

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