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EM488M1644LBB-75FE Datasheet(PDF) 1 Page - Eorex Corporation |
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EM488M1644LBB-75FE Datasheet(HTML) 1 Page - Eorex Corporation |
1 / 19 page eorex Preliminary EM488M1644LBB May. 2007 www.eorex.com 128Mb (2M ×4Bank×16) Synchronous DRAM Features • Fully Synchronous to Positive Clock Edge • Single 1.8V ±0.1V Power Supply • LVCMOS Compatible with Multiplexed Address •Programmable Burst Length –1/2/4/8/ full Page • Programmable CAS Latency (C/L) - 2 or 3 • Data Mask (DQM) for Read / Write Masking • Programmable Wrap Sequence – Sequential (B/L = 1/2/4/8/full Page) – Interleave (B/L = 1/2/4/8) • Burst Read with Single-bit Write Operation • Deep Power Down Mode. • Auto Refresh and Self Refresh • Special Function Support. – PASR (Partial Array Self Refresh) – Auto TCSR (Temperature Compensated Self Refresh) • Programmable Driver Strength Control – Full Strength or 1/2, 1/4 of Full Strength • 4,096 Refresh Cycles / 64ms (15.625us) Description The EM488M1644LBB is Synchronous Dynamic Random Access Memory (SDRAM) organized as 2Meg words x 4 banks by 16 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 128Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 1.8V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVCMOS. Available packages: TFBGA-54B(8mmx8mm) Ordering Information Part No Organization Max. Freq Package Grade Pb EM488M1644LBB-75F 8M X 16 133MHz @CL3 TFBGA -54B Commercial Free EM488M1644LBB-75FE 8M X 16 133MHz @CL3 TFBGA -54B Extend temp. Free * EOREX reserves the right to change products or specification without notice. 1/19 |
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