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M27V102-150K1TR Datasheet(PDF) 2 Page - STMicroelectronics |
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M27V102-150K1TR Datasheet(HTML) 2 Page - STMicroelectronics |
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2 / 15 page  Q6 Q5 Q4 Q11 Q8 VSS Q7 Q10 Q9 A12 A8 A11 A10 A6 A13 A9 VSS A7 A2 Q1 Q0 A0 G A1 A5 NC P E Q12 VPP VCC Q15 AI01913 M27V102 8 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Q3 Q2 Q14 Q13 A4 A3 40 39 38 37 36 35 34 33 A14 A15 Figure 2A. DIP Pin Connections AI01914 A11 A7 23 Q6 Q5 Q4 Q12 Q8 VSS NC Q11 Q10 12 A9 1 VSS A12 A5 44 M27V102 A13 NC A6 34 Q9 A10 A8 Q7 Figure 2B. LCC Pin Connections Warning: NC = Not Connected. For application where the content is programmed only one time and erasure is not required, the M27V102 is offered in PDIP40, PLCC32 and TSOP40 (10 x 14 mm) packages. DEVICE OPERATION The operating modes of the M27V102 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for Vpp and 12V on A9 for Electronic Signature. Read Mode The M27V102 has two control functions, both of which must be logically active in order to obtaindata at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tOE from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV- tGLQV. Warning: NC = Not Connected. DQ6 DQ3 DQ2 DQ13 DQ8 DQ7 DQ10 DQ9 A14 A8 A11 A10 A4 A15 A9 G A7 A2 DQ1 DQ0 A0 A1 A3 NC P E DQ14 VPP VCC DQ15 AI01915 M27V102 (Normal) 10 1 11 20 21 30 31 40 VSS A12 A6 A13 A5 DQ12 DQ4 DQ11 DQ5 VSS Figure 2C. TSOP Pin Connections Warning: NC = Not Connected. DESCRIPTION (cont’d) 2/15 M27V102 |
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Similar Description - M27V102-150K1TR |
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