EM44AM1684LBA-5F datasheet(10/29 Pages) EOREX

Part #	EM44AM1684LBA-5F

Description	256Mb (4M횞4Bank횞16) Double DATA RATE 2 SDRAM

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Manufacturer	EOREX [Eorex Corporation]

Direct Link	http://www.eorex.com

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10 / 29 page

eorex

EM44AM1684LBA

Jul. 2006

www.eorex.com

AC Operating Test Characteristics

(VDD=1.8V±0.1V, TA=0°C ~85°C)

-3

-37

-5

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Units

tDQCK

DQ output access from

CLK,/CLK

-0.45

+0.45

-0.5

+0.5

-0.6

+0.6

ns

tDQSCK

DQS output access time from

CLK,/CLK

-0.4

+0.4

-0.45

+0.45

-0.5

+0.5

ns

tCL,tCH

CL low/high level width

0.45

0.55

0.45

0.55

0.45

0.55

tCK

Clock Cycle Time

3

8

3.75

8

5

8

ns

tDS

DQ and DM setup time

0.1

-

0.1

-

0.15

-

ns

tDH

DQ and DM hold time

0.18

-

0.23

-

0.28

-

ns

tDIPW

DQ and DM input pulse width

for each input

0.35

-

0.35

-

0.35

-

tCK

tHZ

Data out high impedance time

from CLK,/CLK

-

+0.45

-

+0.5

-

+0.6

ns

tLZ

Data out low impedance time

from CLK,/CLK

-0.45

+0.45

-0.5

+0.5

-0.6

+0.6

ns

tDQSQ

DQS-DQ skew for associated

DQ signal

-

0.24

-

0.3

-

0.35

ns

tQSH

Data hold skew factor

-

0.34

-

0.4

-

0.45

ns

tDQSS

Write command to first

latching DQS transition

-0.25

+0.25

-0.25

+0.25

-0.25

+0.25

tCK

tDQSL,tDQSH

DQS Low/High input pulse

width

0.35

-

0.35

-

0.35

-

tCK

tDSL,tDSH

DQS input valid window

0.2

-

0.2

-

0.2

-

tCK

tMRD

Mode Register Set command

cycle time

2

-

2

-

2

-

tCK

tWPRES

Write Preamble setup time

0

-

0

-

0

-

ns

tWPRE

Write Preamble

0.35

-

0.35

-

0.35

-

tCK

tWPST

Write Postamble

0.4

0.6

0.4

0.6

0.4

0.6

tCK

tIS

Address/control input setup

time

0.2

-

0.25

-

0.35

-

ns

tIH

Address/control input hold

time

0.28

-

0.38

-

0.48

-

ns

tRPRE

Read Preamble

0.9

1.1

0.9

1.1

0.9

1.1

tCK

10/29

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