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TVP5146M2PFP_0708 Datasheet(PDF) 70 Page - Texas Instruments |
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TVP5146M2PFP_0708 Datasheet(HTML) 70 Page - Texas Instruments |
70 / 108 page Functional Description 62 SLES141B—August 2007 TVP5146M2PFP 2.11.61 F-bit and V-bit Control 2 Register Subaddress 75h Default 16h 7 6 5 4 3 2 1 0 Reserved Fast lock F and V [1:0] Phase det HPLL Fast lock: Enable fast lock where vertical PLL is reset and a 2-second timer is initialized when vertical lock is lost; during timeout, the detected input VS is output. 0 = Disabled 1 = Enabled (default) F and V Lines per Frame F Bit V Bit Standard ITU-R BT 656 ITU-R BT 656 00 = Nonstandard-even Forced to 1 Switch at field boundary 00 = Nonstandard-odd Toggles Switch at field boundary 01 = Standard ITU-R BT 656 ITU-R BT 656 01 = Nonstandard Toggles Switch at field boundary 10 = Standard ITU-R BT 656 ITU-R BT 656 10 = Nonstandard Pulsed mode Switch at field boundary 11 = Reserved Phase det: Enable integral-window phase detector 0 = Disabled 1 = Enabled (default) HPLL: Enable horizontal PLL to free run 0 = Disabled (default) 1 = Enabled 2.11.62 VCR Trick Mode Control Register Subaddress 76h Default 8Ah 7 6 5 4 3 2 1 0 Switch header Horizontal shake threshold [6:0] Switch header: When in VCR trick mode, the header noisy area around the head switch is skipped. 0 = Disabled 1 = Enabled (default) Horizontal shake threshold [6:0]: 000 0000 = Zero threshold 000 1010 = 0Ah (default) 111 1111 = Largest threshold |
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Similar Description - TVP5146M2PFP_0708 |
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