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TPA5050RSATG4 Datasheet(PDF) 7 Page - Texas Instruments |
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TPA5050RSATG4 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 21 page www.ti.com GENERAL I2C OPERATION Register(N) 8-BitDatafor 8-BitDatafor Register(N+1) SINGLE-AND MULTIPLE-BYTE TRANSFERS TPA5050 SLOS492B – MAY 2006 – REVISED MAY 2007 APPLICATION INFORMATION (continued) The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 5. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then wait for an acknowledge condition. The TPA5050 holds SDA low during acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pull-up resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. When the bus level is 5 V, pull-up resistors between 1 k Ω and 2 kΩ in value must be used. Figure 5. Typical I2C Sequence There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 5. The 7-bit address for the TPA5050 is selectable using the 3 address pins (ADD2, ADD1, ADD0). Table 1 lists the 8 possible slave addresses. Table 1. I2C Slave Address SELECTABLE ADDRESS BITS FIXED ADDRESS (4 MSB bits) ADD2 ADD1 ADD0 1101 0 0 0 1101 0 0 1 1101 0 1 0 1101 0 1 1 1101 1 0 0 1101 1 0 1 1101 1 1 0 1101 1 1 1 The serial control interface supports both single-byte and multi-byte read/write operations for all registers. During multiple-byte read operations, the TPA5050 responds with data, a byte at a time, starting at the register assigned, as long as the master device continues to respond with acknowledges. 7 Submit Documentation Feedback |
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