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M27V102-100N1TR Datasheet(PDF) 8 Page - STMicroelectronics |
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M27V102-100N1TR Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 15 page tAVPL VALID AI00706 A0-A15 Q0-Q15 VPP VCC P G DATA IN DATA OUT E tQVPL tVPHPL tVCHPL tPHQX tPLPH tGLQV tQXGL tELPL tGHQZ tGHAX PROGRAM VERIFY Figure 6. Programming and Verify Modes AC Waveforms PRESTO II Programming Algorithm PRESTO II Programming Algorithm allows pro- gramming of the whole array with a guaranteed margin, in a typical time of 6.5 seconds. Program- ming with PRESTO II consists of applying a se- quenceof 100 µs programpulses toeach worduntil a correct verify occurs (see Figure 7). During pro- gramming and verify operation, a MARGIN MODE circuit is automaticallyactivated in order to guaran- tee that each cell is programmed with enough margin. No overprogram pulse is applied since the verify in MARGIN MODE at VCC much higher than 3.6V provides necessary margin to each pro- grammed cell. Program Inhibit Programming of multiple M27V102s in parallel with different data is also easily accomplished. Except for E, all like inputs including G of the parallel M27V102 may be common. A TTL low level pulse applied to a M27V102’sP input, with E low and VPP at 12.75V, will program that M27V102. A high level E input inhibits the other M27V102s from being programmed. Program Verify A verify (read) should be performed on the pro- grammed bits to determine that they were correctly programmed. The verify is accomplished with E AI00707C n= 0 Last Addr VERIFY P = 100 µs Pulse ++n =25 ++ Addr VCC = 6.25V, VPP = 12.75V FAIL CHECK ALL WORDS 1st: VCC =6V 2nd: VCC = 4.2V YES NO YES NO YES NO Figure 7. Programming Flowchart 8/15 M27V102 |
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