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SN65LVDS105PW Datasheet(PDF) 1 Page - Texas Instruments |
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SN65LVDS105PW Datasheet(HTML) 1 Page - Texas Instruments |
1 / 27 page www.ti.com FEATURES DESCRIPTION 4Z 4Y 3Z 3Y 2Z 2Y 1Z 1Y EN1 EN2 A ’LVDS104 EN4 logic diagram (positive logic) EN3 B 4Z 4Y 3Z 3Y 2Z 2Y 1Z 1Y EN1 EN2 A ’LVDS105 EN4 EN3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 EN1 EN2 EN3 VCC GND A B EN4 1Y 1Z 2Y 2Z 3Y 3Z 4Y 4Z SN65LVDS104 D OR PW PACKAGE (Marked as LVDS104) (TOP VIEW) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 EN1 EN2 EN3 VCC GND A NC EN4 1Y 1Z 2Y 2Z 3Y 3Z 4Y 4Z SN65LVDS105 D OR PW PACKAGE (Marked as LVDS105) (TOP VIEW) SN65LVDS104 SN65LVDS105 SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS • Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Operates From a Single 3.3-V Supply • Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100- Ω Load • Propagation Delay Time – SN65LVDS105 – 2.2 ns (Typ) – SN65LVDS104 – 3.1 ns (Typ) • LVTTL Levels Are 5-V Tolerant • Electrically Compatible With LVDS, PECL, LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT, SSTL, or HSTL Outputs With External Networks • Driver Outputs Are High Impedance When Disabled or With VCC <1.5 V • Bus-Pin ESD Protection Exceeds 16 kV • SOIC and TSSOP Packaging The SN65LVDS104 and SN65LVDS105 are a differ- ential line receiver and a LVTTL input (respectively) connected to four differential line drivers that im- plement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644 is a data signaling technique that offers low-power, low-noise coupling, and switching speeds to transmit data at relatively long distances. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.) The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. Having the drivers integrated into the same substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input. This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 1999–2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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