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M24164-MN1T Datasheet(PDF) 7 Page - STMicroelectronics |
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M24164-MN1T Datasheet(HTML) 7 Page - STMicroelectronics |
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7 / 21 page  7/21 M24164 that is, the most significant memory address bits are the same. If more bytes are sent than will fit up to the end of the row, a condition known as ‘roll- over’ occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. If Write Control (WC) is High, the contents of the addressed memory loca- tion are not modified, and each data byte is fol- lowed by a NoAck. After each byte is transferred, the internal byte address counter (the 4 least sig- nificant address bits only) is incremented. The transfer is terminated by the bus master generat- ing a Stop condition. Figure 8. Write Mode Sequences with WC=0 (data write enabled) BYTE WRITE DEV SEL BYTE ADDR DATA IN WC PAGE WRITE DEV SEL BYTE ADDR DATA IN 1 DATA IN 2 WC DATA IN 3 AI02804 PAGE WRITE (cont'd) WC (cont'd) DATA IN N ACK R/W ACK ACK ACK ACK ACK ACK R/W ACK ACK |
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