7
0832F–HIREL–02/07
e2v semiconductors SAS 2007
PC7410
– Load folding to fold new dL1 misses into older outstanding load and store misses to the
same line
– Store miss merging for multiple store misses to the same line. Only coherency action taken
(i.e., address only) for store misses merged to all 32 bytes of a cache line (no data tenure
needed)
– Two-entry finished store queue and four-entry completed store queue between load/store
unit and dL1
– Separate additional queues for efficient buffering of outbound data (castouts, write throughs,
etc.) from dL1 and L2
• Bus Interface
– MPX bus extension to 60X processor interface
– Mode-compatible with 60x processor interface
– 32-bit address bus
– 64-bit data bus
– Bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x,
8x, 9x supported
– Selectable interface voltages of 1.8V, 2.5V and 3.3V
• Power Management
– Low-power design with thermal requirements very similar to PC740 and PC750
– Low voltage 1.8V or 1.5V processor core
– Selectable interface voltages of 1.8V can reduce power in output buffers
– Three static power saving modes: doze, nap, and sleep
– Dynamic power management
• Testability
– LSSD scan design
– IEEE 1149.1 JTAG interface
– Array Built-in Self Test (ABIST) – factory test only
– Redundancy on L1 data arrays and L2 tag arrays
• Reliability and Serviceability
– Parity checking on 60x and L2 cache buses
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