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FDL300E/FDL300D (Preliminary) Revision P13
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contained in this document. Specifications are subject to change without notice.
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FDL300E/FDL300D
Page 5
RECEIVER ELECTRICAL CHARACTERISTICS
Parameter
Minimum
Typical
Maximum
Unit
Vcc
3.0
3.3
3.6
V
Icc (Normal Operation)
45
mA
Icc - Sleep State
20
uA
Output Impedence Between D and D
100
Ω
Offset Voltage for LVDS
1.2
V
Differential Output Voltage (LVDS)
300
400
mV
SD (Signal Detect) On Output Voltage
2.4
V
SD (Signal Detect) Off Output Voltage
0
0.4
V
SD (Signal Detect) Assert Level
-28
-27
-24
dBm
SD (Signal Detect) Deassert Level
-32
-29
-24.5
dBm
SD (Signal Detect) Assert Time
0.6
5
100
us
SD (Signal Detect) Deassert Time
0.6
5
100
us
High Level Output Voltage
1.475
V
Low Level Output Voltage
0.925
V
Maximum Systematic Jitter,
1200
ps p-p
Electrical Output at TP4 (S200)[1]
Maximum Random Jitter,
700
ps p-p
Electrical Output at TP4 (S200)[1]
Note:
1. TP4, test point 4, is the electical interface of the receiver which corresponds to the standard as set in IEEE 1394b and IDB-1394 standards.