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MM24512-WBN5T Datasheet(PDF) 9 Page - STMicroelectronics |
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MM24512-WBN5T Datasheet(HTML) 9 Page - STMicroelectronics |
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9 / 24 page  9/24 M24512 ed, the device replies with Ack. The bus master terminates the transfer by generating a Stop con- dition, as shown in Figure 7. Page Write The Page Write mode allows up to 128 bytes to be written in a single Write cycle, provided that they are all located in the same ’row’ in the memory: that is, the most significant memory address bits (b15-b7) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become overwritten in an implemen- tation dependent way. The bus master sends from 1 to 128 bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. If Write Control (WC) is High, the contents of the addressed memory loca- tion are not modified, and each data byte is fol- lowed by a NoAck. After each byte is transferred, the internal byte address counter (the 7 least sig- nificant address bits only) is incremented. The transfer is terminated by the bus master generat- ing a Stop condition. Figure 7. Write Mode Sequences with WC=0 (data write enabled) BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN WC PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1 WC DATA IN 2 AI01106C PAGE WRITE (cont'd) WC (cont'd) DATA IN N ACK R/W ACK ACK ACK ACK ACK ACK ACK R/W ACK ACK |
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