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MM24128-BWMN5T Datasheet(PDF) 2 Page - STMicroelectronics

Part # MM24128-BWMN5T
Description  256/128 Kbit Serial I짼C Bus EEPROM Without Chip Enable Lines
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

MM24128-BWMN5T Datasheet(HTML) 2 Page - STMicroelectronics

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M24256, M24128
2/17
serial interface that uses a bi-directional data bus
and serial clock. The memory carries a built-in 4-
bit unique Device Type Identifier code (1010) in
accordance with the I2C bus definition.
The memory behaves as a slave device in the I2C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory in-
serts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and af-
ter a NoAck for READ.
Power On Reset: VCC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
write operations during power up, a Power On Re-
set (POR) circuit is included. The internal reset is
held active until the VCC voltage has reached the
POR threshold value, and all operations are dis-
abled – the device will not respond to any com-
mand. In the same way, when VCC drops from the
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any command. A stable and valid VCC
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a slow-
Figure 2A. DIP Connections
Note: 1. NC = Not Connected
SDA
VSS
SCL
WC
NC
NC
VCC
NC
AI01883
M24256
M24128
1
2
3
4
8
7
6
5
Figure 2B. SO Connections
Note: 1. NC = Not Connected
1
AI01884
2
3
4
8
7
6
5
SDA
VSS
SCL
WC
NC
NC
VCC
NC
M24256
M24128
Table 2. Absolute Maximum Ratings 1
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. IPC/JEDEC J-STD-020A
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500
Ω, R2=500 Ω)
Symbol
Parameter
Value
Unit
TA
Ambient Operating Temperature
–40 to 125
°C
TSTG
Storage Temperature
–65 to 150
°C
TLEAD
Lead Temperature during Soldering
PDIP: 10 seconds
SO: 20 seconds (max) 2
260
235
°C
VIO
Input or Output range
–0.6 to 6.5
V
VCC
Supply Voltage
–0.3 to 6.5
V
VESD
Electrostatic Discharge Voltage (Human Body model) 3
4000
V


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