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MM24256-AWDL6T Datasheet(PDF) 3 Page - STMicroelectronics |
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MM24256-AWDL6T Datasheet(HTML) 3 Page - STMicroelectronics |
3 / 20 page 3/20 M24256-A line packages. The M24256-A is also available in a chip-scale (SBGA) package. These memory devices are compatible with the I2C extended memory standard. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The memory carries a built-in 4- bit unique Device Type Identifier code (1010) in accordance with the I2C bus definition. The memory behaves as a slave device in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START condition, generated by the bus master. The START condition is followed by a Device Select Code and RW bit (as described in Table 3), terminated by an acknowledge bit. When writing data to the memory, the memory in- serts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a STOP condition after an Ack for WRITE, and af- ter a NoAck for READ. Power On Reset: VCC Lock-Out Write Protect In order to prevent data corruption and inadvertent write operations during power up, a Power On Re- set (POR) circuit is included. The internal reset is held active until the VCC voltage has reached the POR threshold value, and all operations are dis- abled – the device will not respond to any com- mand. In the same way, when VCC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid VCC must be applied before applying any logic signal. SIGNAL DESCRIPTION Serial Clock (SCL) The SCL input pin is used to strobe all data in and out of the memory. In applications where this line is used by slaves to synchronize the bus to a slow- er clock, the master must have an open drain out- put, and a pull-up resistor must be connected from the SCL line to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchro- nization is not employed, and so the pull-up resis- tor is not necessary, provided that the master has a push-pull (rather than open drain) output. Serial Data (SDA) The SDA pin is bi-directional, and is used to trans- fer data in or out of the memory. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from the SDA bus to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). Chip Enable (E1, E0) These chip enable inputs are used to set the value that is to be looked for on the two least significant bits (b2, b1) of the 7-bit device select code. These inputs must be tied to VCC or VSS to establish the device select code. When unconnected, the E1 and E0 inputs are internally read as VIL (see Table 7 and Table 8) Write Control (WC) The hardware Write Control pin (WC) is useful for protecting the entire contents of the memory from inadvertent erase/write. The Write Control signal is used to enable (WC=VIL) or disable (WC=VIH) write instructions to the entire memory area. When Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I 2C Bus AI01665 VCC CBUS SDA RL MASTER RL SCL CBUS 100 0 4 8 12 16 20 CBUS (pF) 10 1000 fc = 400kHz fc = 100kHz |
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