PIC16F62X

DS80073F-page 10

© 2002 Microchip Technology Inc.

Clarifications/Corrections to the Data

Sheet:

In the Device Data Sheet (DS40300B), the following

clarifications and corrections should be noted.

1.

Module: T1SYNC (Register T1CON)

The bit T1SYNC in the Register T1CON (address

10h) should be asserted logic low (i.e., T1SYNC).

Table 4-1, page 15, and Table 10-2, page 65, of

DS40300B should be listed as follows:

2.

Module: ADEN (Register RCSTA)

The bit ADEN in Register RCSTA (address 18h),

Table 4-1, is misspelled. The correct spelling

should be ADDEN. This also appears in Figures

and text on pages 72, 79, 80, 81, 82, 83, 84, 85, 86

and 89.

TABLE 4-1:

SPECIAL REGISTERS SUMMARY BANK0

TABLE 10-2:

REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR Reset

Value on all

other

Bank 0

10h

T1CON

—

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

18h

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 -00x 0000 -00x

Legend: x = unknown, u = unchanged, - = unimplemented locations, read as ‘0’, q = value depends on condition,

shaded = unimplemented

Note

1:

Other (non power-up) RESETS include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal

operation.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR

Value on

all other

RESETS

10h

T1CON

—

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

Legend:

x

= unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.