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M58BW16FT4T3 Datasheet(PDF) 7 Page - Numonyx B.V |
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M58BW16FT4T3 Datasheet(HTML) 7 Page - Numonyx B.V |
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7 / 87 page  M58BW16F, M58BW32F Description 7/87 1 Description The M58BW16F and M58BW32F are 16 and 32 Mbit non-volatile Flash memories, respectively. They can be erased electrically at block level and programmed in-system on a double-word basis using a 2.7 V to 3.6 V or 2.5 V to 3.3 V VDD supply for the circuit and a 2.4 V to 3.6 V VDDQ supply voltage for the input and output buffers. In the rest of the document the M58BW16F and M58BW32F will be referred to as M58BWxxF unless otherwise specified. The devices support Asynchronous (Latch Controlled and Page Read) and Synchronous Bus operations. The Synchronous Burst Read interface allows a high data transfer rate controlled by the Burst Clock signal, K. It is capable of bursting fixed or unlimited lengths of data. The burst type, latency and length are configurable and can be easily adapted to a large variety of system clock frequencies and microprocessors. All write operations are asynchronous. On power-up the memory defaults to Read mode with an Asynchronous Bus. The device features an asymmetrical block architecture: ● The M58BW32F has an array of 62 main blocks of 512 Kbits each, plus 4 large parameter blocks of 128 Kbits each and 8 small parameter blocks of 64 Kbits each. The large and small parameter blocks are located either at the top (M58BW32FT) or at the bottom (M58BW32FB) of the address space. The first large parameter block is referred to as boot block and can be used either to store a boot code or parameters. The memory array organization is detailed in Table 2: M58BW32F top boot block addresses and Table 3: M58BW32F bottom boot block addresses. ● The M58BW16F has an array of 8 parameter blocks of 64 Kbits each and 31 main blocks of 512 Kbits each. In the M58BW16FT the parameter blocks are located at the top of the address space whereas in the M58BW16FB, they are located at the bottom. The memory array organization is detailed in Table 4: M58BW16F top boot block addresses and Table 5: M58BW16F bottom boot block addresses. Program and Erase commands are written to the command interface of the memory. An on- chip Program/Erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a Program or Erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. Erase can be suspended in order to perform either Read or Program in any other block, and then resumed. Program can be suspended to Read data in any other block, and then resumed. Each block can be programmed and erased over 100,000 cycles. |
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