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M45PE16-VMW6TP Datasheet(PDF) 10 Page - Numonyx B.V |
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M45PE16-VMW6TP Datasheet(HTML) 10 Page - Numonyx B.V |
10 / 45 page SPI modes M45PE16 10/45 3 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: ● CPOL=0, CPHA=0 ● CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 4, is the clock polarity when the bus master is in Stand-by mode and not transferring data: ● C remains at 0 for (CPOL=0, CPHA=0) ● C remains at 1 for (CPOL=1, CPHA=1) Figure 3. Bus master and memory devices on the SPI bus 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate. Figure 3 shows an example of three devices connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, the other devices are high impedance. The pull-up resistor R (represented in Figure 3) ensures that no device is selected if the Bus Master leaves the S line in the high impedance state. In applications where the Bus Master might enter a state where all inputs/outputs SPI lines are in high impedance at the same time (for example, if the Bus Master is reset during the transmission of an instruction), the clock line (C) must be connected to an external pull- down resistor so that, if all inputs/outputs become high impedance, the C line is pulled Low (while the S line is pulled High). This ensures that S and C do not become High at the same time, and so, that the tSHCH requirement is met. AI12836b SPI Bus Master SPI Memory Device SDO SDI SCK CQD S SPI Memory Device CQD S SPI Memory Device CQD S CS3 CS2 CS1 SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) W HOLD W HOLD W HOLD RR R VCC VCC VCC VCC VSS VSS VSS VSS R |
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