M39P0R9080E4, M39P0R1080E4

Signal descriptions

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2.1.7

Flash memory Reset (A-RP)

memory is in reset mode: the outputs are high impedance and the current consumption is

device enters asynchronous read mode, but a negative transition of Chip Enable or Latch

Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V

datasheet).

2.1.8

Flash memory Deep Power-Down (A-DPD)

The Deep Power-Down input is used to put the Flash memory in deep power-down mode.

When the Flash memory is in standby mode and the Enhanced Configuration Register bit

ECR15 is set, asserting the Deep Power-Down input causes the memory to enter the deep

power-down mode.

When the device is in the deep power-down mode, the memory cannot be modified and the

data is protected.

The polarity of the A-DPD pin is determined by ECR14. The Deep Power-Down input is

active Low by default.

2.1.9

Flash memory Latch Enable (A-L)

The Latch Enable input latches the address bits on its rising edge. The address latch is

Enable can be kept Low (also at board level) when the Latch Enable function is not required

or supported.

2.1.10

Flash memory Clock (A-K)

The clock input synchronizes the memory to the microcontroller during synchronous read

ignored during asynchronous read and in write operations.

2.1.11

Flash memory Wait (A-WAIT)

Wait is an output signal used during synchronous read to indicate whether the data on the

one data cycle in advance.

2.1.12

the main power supply for all operations (read, program and erase).