M39P0R8070E2, M39P0R9070E2

Signal descriptions

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2.5

The Output Enable input controls data outputs during the Bus Read operation of the

memory.

2.6

The Write Enable input controls the Bus Write operation of the Flash memory’s Command

Interface. The data and address inputs are latched on the rising edge of Chip Enable or

Write Enable whichever occurs first.

2.7

Write Protect is an input that gives an additional hardware protection for each block. When

and the Locked-Down blocks can be locked or unlocked. (See M58PR512J datasheet for

details).

2.8

The Reset input provides a hardware reset of the memory. When

current consumption is reduced to the Reset Supply Current

in normal operation. Exiting reset mode the device enters asynchronous read mode, but a

negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs.

The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied

2.9

The Deep Power-Down input is used to put the Flash memory in Deep Power-Down mode.

When the Flash memory is in Standby mode and the Enhanced Configuration Register bit

ECR15 is set, asserting the Deep Power-Down input will cause the memory to enter the

Deep Power-Down mode.

When the device is in the Deep Power-Down mode, the memory cannot be modified and the

data is protected.

Low by default.