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M36W0R604040T1ZAQE Datasheet(PDF) 10 Page - Numonyx B.V |
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M36W0R604040T1ZAQE Datasheet(HTML) 10 Page - Numonyx B.V |
10 / 22 page Signal descriptions M36W0R6040T1, M36W0R604BT1 10/22 2 Signal descriptions See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connect-ed to this device. 2.1 Address Inputs (A0-A19) Addresses A0-A19 are common inputs for the Flash Memory and PSRAM components. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Flash memory Program/Erase Controller, and they select the cells to access in the PSRAM. The Flash memory is accessed through the Chip Enable signal (E F) and through the Write Enable (W F) signal, while the PSRAM is accessed through two Chip Enable signals (E1 P and E2P) and the Write Enable signal (WP). 2.2 Address Inputs (A20-A21) Addresses A20-A21 are inputs for the Flash memory component only. The Flash memory is accessed through the Chip Enable signals (E F) and through the Write Enable (WF) signal. 2.3 Data Input/Output (DQ0-DQ15) For the Flash memory, the Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Write Bus operation. For the PSRAM, the Upper Byte Data Inputs/Outputs carry the data to or from the upper part of the selected address during a Write or Read operation, when Upper Byte Enable (UBP) is driven Low. Likewise, the Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the selected address during a Write or Read operation, when Lower Byte Enable (LBP) is driven Low. 2.4 Flash Chip Enable (EF) The Chip Enable inputs activate the memory control logics, input buffers, decoders and sense amplifiers. When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. 2.5 Flash Output Enable (GF) The Output Enable pins control data outputs during Flash memory Bus Read operations. |
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