M36P0R9070E0

Signal descriptions

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2.10

memory is in Reset mode: the outputs are high impedance and the current consumption is

device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch

Enable is required to ensure valid data outputs.

The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied

2.11

The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted

Power-down mode.

2.12

device is in Write mode and Write operations can be performed either to the configuration

registers or to the memory array.

2.13

be achieved with the common I/O data bus.

2.14

DQ15) to or from the upper part of the selected address during a Write or Read operation.

2.15

DQ7) to or from the lower part of the selected address during a Write or Read operation.

bus from receiving or transmitting data. Although the device will seem to be deselected, it

2.16

Configuration Register (RCR) or the Bus configuration register (BCR).