Preliminary Data

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

November 2007

Rev 0.2

1/22

1

M36L0T7050T2

M36L0T7050B2

128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory

and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package

Feature summary

– 1 die of 128 Mbit (8Mb x16, Multiple Bank,

Multi-level, Burst) Flash Memory

– 1 die of 32 Mbit (2Mb x16) Pseudo SRAM

– Manufacturer Code: 20h

– Device Code (Top Flash Configuration)

M36L0T7050T2: 88C4h

– Device Code (Bottom Flash Configuration)

M36L0T7050B2: 88C5h

Flash memory

– Synchronous Burst Read mode: 52MHz

– Random Access: 85ns

– 2.5µs typical Word program time using

Buffer Enhanced Factory Program

command

– Multiple Bank Memory Array: 8 Mbit Banks

– Parameter Blocks (Top or Bottom location)

– program/erase in one Bank while read in

others

– No delay between read and write

operations

– All blocks locked at power-up

– Any combination of blocks can be locked

with zero latency

–WP for Block Lock-Down

– 64 bit unique device number

– 2112 bit user programmable OTP Cells

PSRAM

– Deep Power-Down

– 4 Mbit Partial Array Refresh

– 8 Mbit Partial Array Refresh

TFBGA88 (ZAQ)

8 x 10mm

FBGA

www.numonyx.com