M25P05-AVMN6TP datasheet(8/52 Pages) NUMONYX

Part #	M25P05-AVMN6TP

Description	512 Kbit, serial Flash memory, 50 MHz SPI bus interface

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Manufacturer	NUMONYX [Numonyx B.V]

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Signal descriptions

M25P05-A

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2

Signal descriptions

2.1

Serial Data output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the

falling edge of Serial Clock (C).

2.2

Serial Data input (D)

This input signal is used to transfer data serially into the device. It receives instructions,

addresses, and the data to be programmed. Values are latched on the rising edge of Serial

Clock (C).

2.3

Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data

present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on

Serial Data output (Q) changes after the falling edge of Serial Clock (C).

2.4

Chip Select (S)

When this input signal is High, the device is deselected and Serial Data output (Q) is at high

impedance. Unless an internal program, erase or write status register cycle is in progress,

the device will be in the standby mode (this is not the deep power-down mode). Driving Chip

Select (S) Low enables the device, placing it in the active power mode.

After power-up, a falling edge on Chip Select (S) is required prior to the start of any

instruction.

2.5

Hold (HOLD)

The Hold (HOLD) signal is used to pause any serial communications with the device without

deselecting the device.

During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data

input (D) and Serial Clock (C) are don’t care.

To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.

2.6

Write Protect (W)

The main purpose of this input signal is to freeze the size of the area of memory that is

protected against program or erase instructions (as specified by the values in the BP1 and

BP0 bits of the status register).

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M25P05-AVMN6TP Datasheet(PDF) 8 Page - Numonyx B.V

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