SN74AHC125Q

QUADRUPLE BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SGDS015 – FEBRUARY 2002

1

POST OFFICE BOX 655303

Requirements

Can Be Supported Along With

Major-Change Approval

CMOS) Process

JESD 17

description

The SN74AHC125Q is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each

output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate

passes the data from the A input to its Y output.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

40

°Cto125°C

SOIC – D

Tape and reel

SN74AHC125QDR

AHC125Q

–40

°C to 125°C

TSSOP – PW

Tape and reel

SN74AHC125QPWR

HA125Q

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

FUNCTION TABLE

(each buffer)

INPUTS

OUTPUT

OE

A

Y

L

H

H

L

LL

H

X

Z

Copyright

 2002, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments.

D OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1OE

1A

1Y

2OE

2A

2Y

GND

4OE

4A

4Y

3OE

3A

3Y