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ST7FLCD1 Datasheet(PDF) 11 Page - STMicroelectronics |
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ST7FLCD1 Datasheet(HTML) 11 Page - STMicroelectronics |
11 / 95 page 11/95 ST7FLCD1 General Information 1.6 Memory Map Note:1. Refer to Table 2: Hardware Register Memory Map. 2. Area FF00h to FFDFh is reserved in the event of ICD use. (For more information, refer to Application Note 1581.) 3. Refer to Table 3: Interrupt Vector Map. Figure 4: Program Memory Map Table 2: Hardware Register Memory Map (Sheet 1 of 3) Address Block Register Register Name Reset Status Remarks 0000h NAME NAMER Circuit Name Register 00h Read 0001h MISC MISCR Miscellaneous Register 00h R/W 0002h Port A PADR Port A Data Register 00h R/W 0003h PADDR Port A Data Direction Register 00h R/W 0004h Port B PBDR Port B Data Register 00h R/W 0005h PBDDR Port B Data Direction Register 00h R/W 0006h Port C PCDR Port C Data Register 00h R/W 0007h PCDDR Port C Data Direction Register 00h R/W 0000h RAM Interrupt & Reset Vectors HW Registers 0040h 16-bit Addressing 003Fh 0FFFh 0100h 01FFh FFE0h FFFFh 1000h 0200h 083Fh 0840h SECTOR 0 SECTOR 1 SECTOR 2 Short Addressing RAM (zero page) Stack EDIDA EDIDB 0600h (See Note 1) (See Note 3) F000h E000h FF00h FFDFh (See Note 2) |
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