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EM77930 Datasheet(PDF) 5 Page - ELAN Microelectronics Corp |
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EM77930 Datasheet(HTML) 5 Page - ELAN Microelectronics Corp |
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5 / 114 page  Contents Product Specification (V1.0) 08.20.2007 • v 8.3 Register Description........................................................................................... 53 8.3.1 Bit Length Register (BLR)................................................................................. 53 8.3.2 Preamble Low Register (PRE-L) ...................................................................... 53 8.3.3 Preamble High Register (PRE-H)..................................................................... 53 8.3.4 Packet Parameter Register (PPR).................................................................... 53 8.3.5 System Control Register 1 (SCR1)................................................................... 55 8.3.6 System Control Register 2 (SCR2)................................................................... 55 8.3.7 System Control Register 3 (SCR3)................................................................... 56 8.3.8 System Control Register 4 (SCR4)................................................................... 58 8.3.9 Transmit FIFO Status Register (TFSR) ............................................................ 58 8.3.10 Receive FIFO Status Register (RFSR)............................................................. 58 8.3.11 Location Control Register (LCR) ...................................................................... 59 8.3.12 Node Identity Register (BIR)............................................................................. 60 8.3.13 Net Identity Register (NIR) ............................................................................... 60 8.3.14 System Status Register (SSR) ......................................................................... 60 8.3.15 Packet Size Register (PSR) ............................................................................. 62 8.3.16 Carrier Sense Register (CSR) .......................................................................... 62 8.4 Interrupt Registers ............................................................................................. 63 8.4.1 Interrupt Enable Register (IER) ........................................................................ 63 8.4.2 Interrupt Identification Register (IIR)................................................................. 64 8.5 List of BB Register Mapping .............................................................................. 65 8.6 MCU BB Control Registers ................................................................................ 66 8.6.1 Control Registers List ....................................................................................... 66 8.6.2 BB Control Example ......................................................................................... 67 9 Universal Serial Bus (USB).......................................................................................69 9.1 Block Diagram.................................................................................................... 69 9.2 USB FIFO Allocation.......................................................................................... 69 9.3 Pin Description................................................................................................... 70 9.4 Timing Diagram of MCU Interface ..................................................................... 71 9.5 USB Device Register Summary ........................................................................ 72 9.5.1 General Control Register (GCNTR).................................................................. 73 9.5.2 Endpoint n Control Register (EP1/2/3CNTR) ................................................... 74 9.5.3 Endpoint Interrupt Event Register (EPINTR).................................................... 74 9.5.4 Endpoint Interrupt Event Enable Register (EPINTE)........................................ 76 9.5.5 State Interrupt Event Register (STAINTR)........................................................ 76 9.5.6 State Interrupt Event Enable Register (STAINTE)............................................ 76 9.5.7 Function Address Register (FAR) ..................................................................... 77 9.5.8 Endpoint 0 RX Token Register (EP0RXTR) ..................................................... 77 9.5.9 Endpoint 0 RX Command/Status Register (EP0RXCSR) ................................ 77 9.5.10 Endpoint 0 TX Command/Status Register (EP0TXCSR) ................................. 78 9.5.11 Endpoint 0 RX Count Register (EP0RXCTR)................................................... 79 9.5.12 Endpoint0 TX Count Register (EP0TXCTR)..................................................... 79 9.5.13 Endpoint 0 RX Data Register (EP0RXDAR)..................................................... 80 |
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