Peak Reducing EMI Solution
W180
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-07156 Rev. *B
Revised October 5, 2005
Features
• Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the
output
• Selectable output frequency range
• Single 1.25% or 3.75% down or center spread output
• Integrated loop filter components
• Operates with a 3.3V or 5V supply
• Low power CMOS design
• Available in 8-pin SOIC (Small Outline Integrated
Circuit)
Key Specifications
Supply Voltages:............................................VDD = 3.3V±5%
or VDD = 5V±10%
Frequency Range:...............................8 MHz < Fin < 28 MHz
Cycle to Cycle Jitter: ........................................ 300 ps (max.)
Selectable Spread Percentage:.................... 1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time:...................................5 ns (max.)
Table 1. Modulation Width Selection
SS%
W180-01, 02, 03
Output
W180-51, 52, 53
Output
0Fin > Fout > Fin – 1.25% Fin + 0.625% > Fin > – 0.625%
1Fin > Fout > Fin – 3.75% Fin + 1.875% > Fin > –1.875%
Table 2. Frequency Range Selection
FS2
FS1
W180 Option#
-01, 51
(MHz)
-02, 52
(MHz)
-03, 53
(MHz)
00
8 < FIN < 10
8 < FIN < 10
N/A
01
10 < FIN < 15 10 < FIN < 15
N/A
10
15 < FIN < 18
N/A
15 < FIN < 18
11
18 < FIN < 28
N/A
18 < FIN < 28
Simplified Block Diagram
Pin Configurations
Spread Spectrum
W180
(EMI suppressed)
3.3V or 5.0V
Oscillator or
Spread Spectrum
W180
(EMI suppressed)
3.3V or 5.0V
XTAL
X1
X2
Reference Input
Input
Output
Output
8
7
6
5
1
2
3
4
CLKIN or X1
NC or X2
GND
SS%
SSON#
FS1
VDD
CLKOUT
8
7
6
5
1
2
3
4
CLKIN or X1
NC or X2
GND
SS%
FS2
FS1
VDD
CLKOUT
SOIC
