W152
Document #: 38-07148 Rev. *A
Page 4 of 8
Absolute Maximum Ratings[3]
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
.
Parameter
Description
Rating
Unit
VDD, VIN
Voltage on any pin with respect to GND
–0.5 to +7.0
V
TSTG
Storage Temperature
–65 to +150
°C
TA
Operating Temperature
0 to +70
°C
TB
Ambient Temperature under Bias
–55 to +125
°C
PD
Power Dissipation
0.5
W
DC Electrical Characteristics: TA =0°C to 70°C, VDD = 3.3V ±10%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
IDD
Supply Current
Unloaded, 100 MHz
40
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
2.0
V
VOL
Output Low Voltage
IOL = 12 mA (-11, -12)
IOL = 8 mA (-1, -2, -3, -4)
0.4
V
VOH
Output High Voltage
IOH = 12 mA (-11, -12)
IOH = 8 mA (-1, -2, -3, -4)
2.4
V
IIL
Input Low Current
VIN = 0V
50
µA
IIH
Input High Current
VIN = VDD
50
µA
AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±10%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
fIN
Input Frequency
Note 4
15
140
MHz
fOUT
Output Frequency
15-pF load[9]
15
140
MHz
tR
Output Rise Time (-1, -2, -3, -4)
0.8V to 0.8V, 15-pF load
2
2.5
ns
Output Rise Time (-11, -12)
0.8V to 0.8V, 15-pF load
1.5
ns
tF
Output Fall Time (-1, -2, -3, -4)
2.0V to 0.8V, 15-pF load
2
2.5
ns
Output Rise Time (-11, -12)
2.0V to 0.8V, 20-pF load
1.5
ns
tICLKR
Input Clock Rise Time[5]
4.5
ns
tICLKF
Input Clock Fall Time[5]
4.5
ns
tPD
FBIN to REF Skew[6, 7]
350
ps
tSK
Output to Output Skew
All outputs loaded equally[11]
215
ps
tD
Duty Cycle
15-pF load[8, 9]
45
50
55
%
tLOCK
PLL Lock Time
Power supply stable
1.0
ms
tJC
Jitter, Cycle-to-Cycle
Note 10
225
ps
Notes:
3.
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4.
Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration). See
Table 1.
5.
Longer input rise and fall time will degrade skew and jitter performance.
6.
All AC specifications are measured with a 50
Ω transmission line.
7.
Skew is measured at VDD/2 on rising edges.
8.
Duty cycle is measured at VDD/2.
9.
For the higher drive -11 and -12, the load is 20 pF.
10. For frequencies above 25 MHz CY - CY = 125 ps.
11. Measured across all outputs. Maximum skew between outputs in the same bank is 100 ps.
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